In recent years, microelectronic technologies around silicon integrated circuits (IC) have been developing rapidly. The development of integrated circuit chips basically follows Moore's Law, that is, the degree of integration for semiconductor chips increases by doubling every 18 months. But as the semiconductor chip integration continues to increase, MOS channel length is also shortened continually. When the MOS transistor channel length becomes very short, short channel effect causes the semiconductor chip performance to decline, or to even fail entirely. Traditional silicon integrated circuit chips are generally fabricated on bulk silicon.
With the start of 90 nm technologies, semiconductor companies have been manufacturing large-scale integrated circuit chips using silicon-on-insulator (SOI) substrates. The SOI integrated circuit chips have the advantages of strong anti-radiation capabilities, easy isolation between devices, small parasitic capacitance, and strong anti-latch-up capabilities. Also, SOI field-effect transistors are excellent at controlling short channel effects, and have superior miniaturization capabilities compared to transistors built on bulk silicon. Therefore, ultra-thin body silicon SOI substrate and full depletion-type field-effect transistors fabricated thereon have great application prospects in future semiconductor integrated circuits.
At the same time, SOI integrated circuit chips, especially SOI full depletion type field-effect transistor integrated circuit chips, also have attendant shortcomings, including floating-body effect and relatively low heat dissipation capacity. Floating-body effects cause certain memory effects in the field-effect transistors, reducing the reliability of IC operation. Thus, forming highly effective body contact in SOI field-effect transistors is an important subject.